Throw Away the Textbook – Redefining AC/DC Power Conversion for Improved Efficiency, Reduced Complexity and Better Performance

Any electronic equipment that connects to a wall socket requires an AC/DC converter to rectify the mains voltage and reduce it to a lower DC level. In some cases the AC/DC converter is embedded in the product itself and in others a dedicated external power supply is used. AC/DC conversion is also at the heart of the adapters used to charge mobile phones, tablets and other portable devices.

Despite their low power nature, the fact that billions of these products are in use means they significantly impact global energy consumption and emissions and that legislation and sustainability initiatives are putting their efficiency under more scrutiny than ever before. What’s more, because many power supplies and devices are left plugged in twenty-four hours a day, seven days a week but only operate at full load for a small percentage of that time, they have long idle periods.

As a result,
there is a growing
recognition of the need
to improve full-load,
low-load and no-load

AC/DC Conversion Today

While there may have been improvements in the components and integration levels, the fundamental circuits and architectures employed in power schemes that convert AC mains voltage to DC have not changed dramatically for many years. Indeed, you can find references to some of today’s most commonly used designs - including flyback converters, forward converters, active clamp flyback (ACF) and LLC and LCC architectures - in textbooks as far back as the fifties.

In particular, the flyback topology is extremely popular in low-power designs due to its versatility, performance and simplicity. In use for over 70 years, this topology generally consists of a primary-side MOSFET, output (secondary) rectifier diode, output capacitor and flyback transformer alongside a few other minor components. Recently, quasi-resonant (QR) flyback architectures have become popular due to their ability to reduce switching losses by lowering the drain-source voltage (VDS) of the primary MOSFET before the turn-on pulse in a very cost-effective way. This has the effect of reducing power losses, ensuring that the MOSFET turns on at the first ‘valley’, thus closer to Zero Voltage Switching conditions. However, the efficiency gains from QR operation are primarily realized in full-load. The second and third valleys are useful in mid loads (but not as good as the first valley), and the hard-switching nature of this topology results in much lower efficiency at light load, when the valleys are completely damped.

QR flyback designs can be further improved by implementing soft or zero-voltage switching (ZVS) in which VDS falls to zero (rather than just a minimum) before the MOSFET is switched. This eliminates overlap between the voltage and current, minimizing losses and EMI.

Active Clamp Flyback AC/DC Converter Circuit (courtesy of ResearchGate)

One further development is the active clamp flyback (ACF) topology that re-uses energy stored in the transformer’s leakage inductance that would traditionally have dissipated in a passive clamp snubber resistor. Delivering this ‘recycled’ energy to the load improves converter efficiency and significantly reduces the peak voltage across the MOSFET during turn-off. By contrast, this approach is extremely expensive (requiring an additional high-side high-voltage fast MOSFET) and, thus,ACF converters are generally used for niche and less cost-sensitive applications.

A New Approach to Flyback Conversion

Now let’s consider a new approach to flyback conversion that, as yet, doesn’t appear in any textbook. Developed by Eggtronic and known as QuarEgg™, among the key benefits of this architecture is its ability to operate with ZVS under all load conditions.

Active Clamp Flyback AC/DC Converter
QuarEgg AC/DC Zero Voltage Switching PD Converter

QuarEgg AC/DC Converter Architecture

As the diagram shows, compared to a conventional QR flyback topology QuarEgg adds an auxiliary low-voltage, low side, low-cost MOSFET connected in parallel to the main rectifying MOSFET. It also eliminates the need for a high-voltage, high-side clamping MOSFET. The main QuarEgg controller is on the secondary side of the converter, which enhances output voltage regulation. The auxiliary MOSFET is high with channel resistance and very low with parasitic capacitance and primarily included as a means of actively forcing the ZVS conditions for the primary power MOSFET across all load conditions. While the converter is switching, the secondary side controller senses the reflected primary MOSFET VDS. When each crest occurs, the auxiliary MOSFET turns on and discharges the drain node so VDS becomes zero, thereby ensuring a ZVS turn-on of the primary MOSFET. The result is lower losses without the need for high-performance GaN FETs. Indeed,a traditional low-cost silicon MOSFET deployed in a QuarEgg topology can work as well as a high-cost GaN FET (and, of course, the same GaN FET can perform better in a QuarEgg topology than standard high-frequency QRtopology).

Additional advantages are the absence of spikes, which leads to reduced stress on the components and better EMI profiles.

QuarEgg Efficiency Improvements Compared to QR Flyback

As the diagram above illustrates, the QuarEgg architecture delivers significant efficiency improvements over conventional QR flyback designs across all output powers. In addition, because QuarEgg requires a smaller bill of materials (BoM), it helps to reduce design complexity, improve reliability and robustness and minimize the form factor and weight of the target application – important points for products such as fast chargers that must deliver high performance and portability.


To find out more about QuarEgg click here

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